Conventionally, a power metal oxide silicon field effect transistor (power MOSFET) is used to provide high voltage circuits for power integrated circuit applications. Various internal parasitic components often impose design and performance limitations on a conventional power MOSFET. Among these parasitic components in a MOSFET transistor, special care must be taken in dealing with a parasitic npn bipolar junction transistor (BJT) formed between the source, the body, and the drain of a MOSFET device. The parasitic current, which flows from the source to the drain and through the body as opposed to a channel, tends to run away, i.e., the more current, the more the bipolar action turns on. For the purpose of reducing parasitic bipolar structure action and improving the device ruggedness, the base resistance of the body or drain to source on-resistance (Rads-on) needs to be minimized. Standard solution is to dope the body as much as possible to reduce base resistance, which reduces current gain of bipolar and forces to push more parasitic current before bipolar turns on since base-emitter voltage VBE is a function of resistance:VBE=Iparasitic×Rbase-local 
For typical BJT devices, VBE is about 0.5V to 0.6V to turn on the bipolar action.
U.S. Pat. No. 5,930,630 discloses a butted trench-contact MOSFET cell structure having a self aligned deep and shallow high-concentration body-dopant regions. A top portion of a lightly doped source region is removed to reduce contact resistance. However, horizontal butted contacts require a lot of space which adversely impacts both cell density and Rds-on. In addition, the trench-contacts can have a high source resistance since a small portion of the N+ source (for NMOS) is contacted by the source metal. Also, for the trench-contact, if the Boron (for NMOS) body contact implant at the bottom of the trench is not vertical, there can be compensation of the N+ source (for NMOS) which results in excessive Rds-on because of increased source resistance.
U.S. Pat. No. 5,684,319 discloses a DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. N+ polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. However, the N+ polysilicon source only improves the source contact, which lowers the resistance, but it has no effect on body region.
It would be desirable to develop a structure which achieves self-aligned source/body contact without using mask, highly rugged and robust structure with low-resistance source and body contact. It would be further desirable to develop a structure which achieves low-thermal budget to realize shallow junctions, compatible with stripe and closed-cell geometries, compatible with standard foundry process, with standard metallization schemes to achieve low contact resistivity, compatible with ultra-small cell-pitch. It would be further desirable to produce a device with a low-cost of manufacture.
It is within this context that embodiments of the present invention arise.